This invention relates, in general, to storage circuits and more particularly to flip flop circuits.
Flip flop circuits are an essential building block for most digital circuits. In fact, flip flops are used in virtually every digital integrated circuit manufactured. Gate arrays and standard cell libraries devote large numbers of their cells to flip flop designs. Most of the flip flops included in a library have minor variations such as a scan input or set/reset options.
It is well known that the speed at which a digital circuit operates is determined by its worst case data path. Flip flop delay can be a large portion of the worst case delay due to their high proclivity of use in digital designs. By concentrating on reducing flip flop delays, it is possible to significantly increase speeds of digital systems.
A flip utilizes a full clock cycle to shift data from the input to the output. One common type of flip flop is a D-flip flop. The D-flip flop (as well as many other flip flop designs) is formed in two distinct sections. The two sections are called a master and a slave section. The master section receives and stores data coupled to the flip flop input during one phase of the clock cycle. The data is shifted from the master section to the slave section during the other phase of the clock cycle. The slave section stores and provides the data at the flip flop outputs.
A latch is commonly used to store data in either the master or slave section of the flip flop. The existing data must be over-written in order for the new data to be stored in the latch. The circuit driving the latch to its new logic state must be strong enough to overcome the latch to write the new data in. Writing data in a latch is a significant portion of the delay in either the master or slave sections.
In general, the slave section has more elements in its data path than the master section. This results in the slave section having a disproportionate amount of delay when compared to the master section. Since most digital systems are clocked using a 50 percent duty cycle clocking scheme the benefits of reducing the master section delay would be negligible until the slave section delay is less than the master section delay. Thus, optimization of the slave section will greatly increase clock rates of a flip flop.
It would be of great benefit if a circuit could be provided which stores data and is easily overwritten while having minimal delay thereby increasing the operating speed of the circuit.